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Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

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3 Author(s)
Dong-Young Chang ; Texas Instrum. Inc., Tucson, AZ, USA ; Gil-Cho Ahn ; Un-Ku Moon

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-μm CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 Vp-p differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.

Published in:

IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:52 ,  Issue: 1 )