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In modern communication systems, the conversion of analog signals into digital form [analog-digital conversion (ADC)] is one of the most critical functions. A fundamental limit of the signal-to-noise ratio (SNR) achievable in this conversion is given by the jitter of the sampling clock. The requirements on the maximum jitter tolerable are typically specified using SNR expressions which hold in the case of an infinite number of samples. However, there are good reasons to investigate the resulting SNR when only a finite number of samples is taken into account. This paper evaluates the effective impact of jitter on the SNR of the ADC process when the observation interval is limited to a finite number of samples. It will be shown that, in this case, the jitter constraints on the sampling clock can be more relaxed.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:51 , Issue: 12 )
Date of Publication: Dec. 2004