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ChipPower: an architecture-level leakage simulator

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5 Author(s)
Yuh-Fang Tsai ; Dept. of Comput. Sci. & Eng., Penn State Univ., University Park, PA, USA ; A. H. Ankadi ; N. Vijaykrishnan ; M. J. Irwin
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Leakage power is projected to be one of the major challenges in future technology generations. The temperature profile, process variation, and transistor count all have strong impact on the leakage power distribution of a processor. We have built a simulator to estimate the dynamic/leakage power for a VLIW architecture considering dynamic temperature feedback and process variation. The framework is based on architecture similar to the Intel Itanium IA64 and is extended to simulate its power when implemented in 65nm technology. Our experimental results show that leakage power will become more than 50% of the power budget in 65nm technology. Moreover, without including the process variation, the total leakage power will be underestimated by as much as 30%.

Published in:

SOC Conference, 2004. Proceedings. IEEE International

Date of Conference:

12-15 Sept. 2004