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FPGA-efficient phase-to-I/Q architecture

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3 Author(s)
I. Janiszewski ; Univ. of Appl. Sci., Darmstadt, Germany ; H. Meuth ; B. Hoppe

A hybrid architecture for digital phase-to-inphase/quadrature (I/Q) at constant-magnitude transformers is presented. The design may be efficiently implemented in FPGA. Starting from the well established co-ordinate rotation digital computer (CORDIC) algorithm, and from look-up table (LUT) schemes, optimum hybrid configurations are derived. Via fully synthesizable HDL models, portability and reusability are ensured. The hybrid LUT/CORDIC architecture allows design partitioning between logic and storage based FPGA resources and is suitable also for multi-phase implementations.

Published in:

SOC Conference, 2004. Proceedings. IEEE International

Date of Conference:

12-15 Sept. 2004