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This paper investigates the problem of global interconnect optimization for intellectual property (IP) based system-on-chip designs. In contrast to previous research, which conducts repeater insertion for global interconnects after the system placement, our approach performs these two steps simultaneously by integrating an interconnect macromodel into the placement procedure. Our macro-model is able to estimate the power dissipation of global interconnects with optimal repeater insertion using the wire length, timing budget, repeater location deviation, and signal activity. Consequently, accurate power dissipation of global interconnects can be used to guide the placement procedure, resulting in high-quality designs. Experimental results have shown that our approach reduces the number of timing-violation paths by more than 80% and achieves up to 11.1% power reduction in comparison with placement schemes based on area or wirelength minimization.