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A leakage-tolerant low-leakage register file with conditional sleep transistor

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3 Author(s)
Agarwal, A. ; Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Kaushik, R. ; Krishnamurthy, R.K.

This paper describes a 256×64b 3-read, 3-write ported leakage tolerant low leakage register file. The local bitline shares a sleep transistor for aggressive bitline leakage reduction/tolerance to enable high fanin bitlines and uses low Vth transistors. The sleep transistor is turned on while accessing the local bitline and conditionally turned off, if the dynamic node should remain high. Simulation results shows that proposed technique achieves 9% improvement in performance with 14× reduction in local bitline leakage (97× reduction as compared to any previously proposed low Vth, leakage tolerant register file) enabling 70% reduction in keeper size, while keeping the same noise robustness as optimized high performance conventional high Vth implementation.

Published in:

SOC Conference, 2004. Proceedings. IEEE International

Date of Conference:

12-15 Sept. 2004