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Application specific instruction memory transformations for power efficient, fault resilient embedded processors

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3 Author(s)
R. Ayoub ; Dept. of CSE, California Univ., San Diego, CA, USA ; P. Petrov ; A. Orailoglu

In this paper we present a coding framework for a low energy instruction bus for embedded processors. The encoder exploits application-specific knowledge regarding program hot-spots to generate codewords that deliver savings in power and to furthermore provide concurrent detection of errors. Power savings can be obtained through the use of codewords that reduce the switching activity on the bus. The analysis shows that generating codewords that prohibit the occurrence of three consecutive transitions in three adjacent lines is fundamental to capturing the worst-case crosstalk faults in the bus lines at run time, thus improving the overall reliability of the bus. The desired codewords can be generated through a set of simple prespecified transformations. The detailed analysis we outline shows that the presented transformations are optimal. The proposed encoding scheme is dynamically reprogrammable, thus targeting code particularities effectively. The restriction to a simple yet efficient set of transformations reduces the required storage capacity and eases reprogrammability while achieving these objectives. Extensive experimental analysis on numerical and DSP codes indicates significant improvements in power savings.

Published in:

SOC Conference, 2004. Proceedings. IEEE International

Date of Conference:

12-15 Sept. 2004