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Many system on chip (SOC) architectures are pushing the analog to digital interface into the RF/IF region. A critical component for such architectures is a band pass analog to digital converter (BPADC). A parallel time interleaved (PTI) delta sigma BPADC is presented which supports RF/IF center frequencies for SOC applications. Three low pass delta sigma modulators sampling at 1 GHz are time interleaved to obtain a BPADC with center frequencies of 1 or 2 GHz in 0.18μm CMOS technology. Resolution depends on bandwidth with 8 bits achievable for a 100 MHz bandwidth and 1 GHz sampling frequencies for the modulators. The BPADC center frequencies, resolution, and bandwidth can be modified by changing the sampling frequency of the modulators or the number of modulators that are time interleaved.
SOC Conference, 2004. Proceedings. IEEE International
Date of Conference: 12-15 Sept. 2004