Cart (Loading....) | Create Account
Close category search window
 

Automatic synthesis of a digital circuit employing an algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

Automatic synthesis of a digital circuit employing an algorithm can be useful for several applications where speed is a vital issue. The digital circuit diagram is provided in AND, OR, NOT and NAND logical bases. The synthesis employs DFG (data flow graph) directed cycles to determine the theoretically optimal insertion of latch setting. The computer program performs the actual synthesis and reduces the effect of human errors. The subalgorithms case is also solved.

Published in:

Electrical and Electronics Engineers in Israel, 2004. Proceedings. 2004 23rd IEEE Convention of

Date of Conference:

6-7 Sept. 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.