Automatic synthesis of a digital circuit employing an algorithm

Automatic synthesis of a digital circuit employing an algorithm can be useful for several applications where speed is a vital issue. The digital circuit diagram is provided in AND, OR, NOT and NAND logical bases. The synthesis employs DFG (data flow graph) directed cycles to determine the theoretically optimal insertion of latch setting. The computer program performs the actual synthesis and reduces the effect of human errors. The subalgorithms case is also solved.