By Topic

Verification and test challenges in SoC designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Duenas, C.A.M. ; Freescale Semicond. Inc., Jaguariuna, Brazil

SoC (system-on-chip) designs have introduced several new challenges for the functional verification and test disciplines. Besides the ever-growing functional complexity, we need to manage from several clock domains and low-power modes to all sorts of IP blocks like processors, complex peripherals, analog functions and different kinds of embedded memories. The reuse of 3rd party IP may help accelerating the design of new products, but it usually does not help the functional verification and it may even add to its complexity. The same die may be used in several packages with a different number of pins and bond-out options. This presentation discusses these and other verification and test challenges. It also describes what tools, techniques and methodologies the industry is currently using to cope with them, and finalizes outlining some future directions.

Published in:

Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on

Date of Conference:

7-11 Sept. 2004