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Integrating cache coherence protocols for heterogeneous multiprocessor system. Part 2

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3 Author(s)
Taeweon Suh ; Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Lee, H.-H.S. ; Blough, D.M.

In this second part of this two-part article, we present two examples of integrating heterogeneous processors and show the limitation of integrating processors without native support for cache coherence. Finally, we discuss the Verilog simulation results of applying our techniques to actual heterogeneous multiprocessor platforms. Experiments with actual heterogeneous multiprocessor platforms on a shared-bus measure the effectiveness of two cache coherence techniques. This integration approach, snoop-hit buffer, and the accompanying region-based cache coherence approach yield significant speedups compared to a pure software solution.

Published in:

Micro, IEEE  (Volume:24 ,  Issue: 5 )

Date of Publication:

Sept.-Oct. 2004

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