Spread spectrum clock generator with delay cell array to reduce the EMI from a high-speed digital system

In high-speed digital systems, most of the EMI from the system is caused by high-speed digital clock drivers and synchronized circuits. In order to reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional spread spectrum clock generator with a phase locked loop (SSCG-PLL) has been implemented by controlling period jitter. However, the conventional SSCG-PLL becomes more difficult to implement at higher clock frequencies, in the GHz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome these problems associated with the random period jitter, we propose a spread spectrum clock generator with a delay cell array (SSCG-DCA), which controls the position of clock transitions. Measurement and simulation have demonstrated that the proposed SSCG-DCA is easier to implement and attenuating the EMI is more effective compared with the conventional SSCG-PLL. The proposed SSCG-DCA was implemented on a chip using a 0.35 /spl mu/m CMOS process and a 9 dB attenuation of the EMI was achieved at 390 MHz.