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Design and implementation of a high speed microprocessor simulator BurstScalar

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2 Author(s)
Nakada, T. ; Toyohashi Univ. of Technol., Japan ; Nakashima, H.

This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the well-known SimpleScalar simulator but its execution speed is accelerated by a computation reuse technique. Each time a loop is iterated, BurstScalar consults its state transition table to examine whether the iteration turns the microarchitectural state into what has already occurred. If the behavior of the iteration matches a state transition table entry, we reuse the complicated computation for out-of-order microarchitectural simulation by simply following the transition arc registered in the table. Moreover in order to minimize the overhead of the reuse, we apply the reuse technique only to loops with enough iterations. This loop selection is performed by an instruction level pre-execution which only costs 1/10 to 1/100 of out-of-order cycle accurate simulation. The evaluation of BurstScalar with SPEC CPU95 benchmarks proves its efficiency showing up to 5.1 and 2.3-fold speedups over SimpleScalar for SPECfp and SPECint respectively, and 2.6 and 1.5-fold in average.

Published in:

Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings. The IEEE Computer Society's 12th Annual International Symposium on

Date of Conference:

4-8 Oct. 2004