Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

ASPEN: towards effective simulation of threads & engines in evolving platforms

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
5 Author(s)

As platforms evolve from employing single-threaded, single-core CPUs to multi-threaded, multi-core CPUs and embedded hardware-assist engines, the simulation infrastructure required for performance analysis of these platforms becomes extremely complex. While investigating hardware/software solutions for server network acceleration (SNA), we encountered limitations of existing simulators for some of these solutions. For example, light weight threading and asynchronous memory copy solutions for SNA could not be modeled accurately and efficiently and hence we developed a flexible trace-driven simulation framework called ASPEN (architectural simulator for parallel engines). ASPEN is based on the use of rich workload traces (RWT), which capture the major events of interest during the execution of a workload on a single-threaded CPU and platform and replaying it a multi-threaded architecture with hardware-assist engines. We introduce the overall ASPEN framework and describe its usage in the context of SNA. We believe that ASPEN is a useful performance tool for future platform architects and performance analysts.

Published in:

Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings. The IEEE Computer Society's 12th Annual International Symposium on

Date of Conference:

4-8 Oct. 2004