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0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR

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4 Author(s)
Li, J. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA ; Gil-Cho Ahn ; Dong-Young Chang ; Un-Ku Moon

An ultra low-voltage CMOS two-stage algorithm ADC incorporating background digital calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 μm CMOS process, achieves 81 dB SFDR at 0.9V and 2MSPS (12MHz clock) after calibration. The ADC operates up to 5MSPS (30MHz clock) with 4dB degradation. The total power consumption is 12mW, and the active die area is 1.4 mm2.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004