A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency

A 1.5V 10-b 50MS/s 2-channel pipeline ADC is described. Amplifiers arc efficiently shared between channels using low-voltage techniques to reduce the power supply. The selected resolution per stage avoids the need of scaling the stages, simplifying the implementation of a low-power design. Measurements from the prototypes fabricated in a 0.18 /spl mu/m CMOS technology exhibit 10b DNL, 9.5b INL and 9.2 effective bits at Nyquist-rate. The chip occupies 1.3 mm/sup 2/ and dissipates only 29 mW at 1.5V.