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SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

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9 Author(s)
Zhang, K. ; Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA ; Bhattacharya, U. ; Chen, Z. ; Hamzaoglu, F.
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A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57 μm2 6T cell with large noise margin down to 0.7V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with sleep transistor. It also has a built-in programmable defect "screen" circuit for high volume manufacturing.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004