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Analysis and design of transceiver circuit and inductor layout for inductive inter-chip wireless superconnect

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5 Author(s)
Miura, N. ; Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan ; Mizoguchi, D. ; Yusof, Y.B. ; Sakurai, T.
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A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by an equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communications distance, transmit power, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive Non-Return-to-Zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35 μm CMOS. Accuracy of the models is verified. Bit error rate is investigated for various inductor layouts and communications distance. The maximum data rate is 1.25Gb/s/channel. Power dissipation is 43mW in the transmitter and 2.6mW in the receiver at 3.3V. If chip thickness is reduced to 30 μm in 90nm device generation, power dissipation will be 1mW/channel or bandwidth will be 1Tb/s/mm2.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004