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A background optimization method for PLL by measuring phase jitter performance

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2 Author(s)
Dosho, S. ; Matsushita Electr. Ind. Co. Ltd., Osaka, Japan ; Yanagisawa, N.

This paper describes a background (BG) optimization method for Phase-Locked-Loop(PLL). Measuring the phase shift of the voltage controlled oscillator(VCO) at each input reference clock, we can determine the phase jitter performance exactly. Using the combination of the global optimization method at initial phase and the local optimization method for background calibration always gives the PLL the smallest jitter performance under any conditions.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004

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