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A 0.6-4.2V low-power configurable PLL architecture for 6 GHz-300 MHz applications in a 90 nm CMOS process

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1 Author(s)
Raha, P. ; Texas Instrum. Inc., Dallas, TX, USA

This paper presents a configurable feed-forward PLL architecture with supply-independent loop dynamics for low power, multiphase clock-generation in power-sensitive DSP cores using dynamic voltage scaling techniques in a 90 nm CMOS process. A four-stage, current-controlled ring-oscillator based PLL is shown to be able to generate 6 GHz-300 MHz frequencies in a 90 nm CMOS process with a power supply range of 1.2-0.6 V. PLL power consumption is 10 mW@5 GHz and 300 uW@500 MHz. The PLL die area is 0.10 mm2.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004