An area-efficient implementation of digital-IF QAM coherent demodulator for software-defined radio receivers

This paper presents a digital-IF QAM coherent demodulator implemented on 0.11-mm/sup 2/ die area. Two independent resampling circuits with second-order digital tracking loops are employed in order to achieve both the carrier and timing recoveries. A coherent demodulator with complete digital synchronization functions achieves a bit-error rate of 10/sup -6/ with an implementation loss of 0.6 dB for uncoded 16-QAM signal. It consumes 16 mW with a 1.8-V supply, working in 80 MHz.