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This paper studies the design tradeoffs to minimize power dissipation of multi-Gbps parallel I/O transmitters. A macromodel of a transmitter that can be optimized for power is presented. Also discussed is a means to consider the impact of deterministic jitter due to on-chip buffering on power dissipation. The model allows analysis that considers varying design constraints, and circuit architectures. The optimization results provide some guidance on the choice of architecture, and data rate to achieve large aggregate I/O bandwidths.