A calibration-free 3V 16b 500kS/s 6mW 0.5mm/sup 2/ ADC with 0.13 /spl mu/m CMOS

A calibration-free 3V 6mW 16-bit 500kS/s cyclic ADC with an active die area of 0.5mm/sup 2/ is implemented in a 0.13 /spl mu/m CMOS. The proposed converter adopts a 2.5-bit/stage cyclic architecture and capacitor layout scheme to achieve improved matching accuracy, the DNL and INL of /spl plusmn/0.90 LSB and /spl plusmn/6.1 LSB, respectively.