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Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement

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3 Author(s)
Mukhopadhyay, S. ; Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Mahmoodi-Meimand, H. ; Roy, K.

In this paper we have analyzed and modeled the failure probabilities (access time failure, read/write stability failure, and hold stability failure in the stand-by mode) of SRAM cells due to process parameter variations. A method to predict the yield of a memory chip designed with a cell is proposed based on the cell failure probability. The developed method can be used in the early stage of a design cycle to optimize the design for yield enhancement.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004