By Topic

1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

15 Author(s)
H. Fujisawa ; Technol. & Dev. Office, Elpida Memory, Inc., Kanagawa, Japan ; M. Nakamura ; Y. Takai ; Y. Koshikawa
more authors

Two circuit techniques of DDR1/DDR2 compatible chip architecture designed for both high-speed and high-density DRAMs are presented. The dual clock input latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase 1-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 ns to 2.15 ns. By using these techniques in combination with a hybrid multi-oxide output buffer, we developed a 175.3 mm2 1Gb SDRAM which operates as a 800-Mb/s/pin DDR2 or 400Mb/s/pin DDR1.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004