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A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

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12 Author(s)
Young-Soo Sohn ; Memory Div., Samsung Electron. Co., Hwasung, South Korea ; Jung-Hwan Choi ; In-Young Chung ; Hoeju Chung
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A 1.8V, 512Mbit Packet-based DRAM with 3.2Gbps/pin was designed for main memory of a game console and graphic application. To have lower power consumption and smaller area in clock generation and distribution, 3-row pad structure with reduced clock loading and PLL with loop zero from voltage offset are used. An analytical equation for estimating the input capacitance of pad with ODT (On-Die Termination) is also presented.

Published in:

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Date of Conference:

17-19 June 2004