A 512Mbit, 3.2Gbps/pin packet-based DRAM with cost-efficient clock generation and distribution scheme

A 1.8V, 512Mbit Packet-based DRAM with 3.2Gbps/pin was designed for main memory of a game console and graphic application. To have lower power consumption and smaller area in clock generation and distribution, 3-row pad structure with reduced clock loading and PLL with loop zero from voltage offset are used. An analytical equation for estimating the input capacitance of pad with ODT (On-Die Termination) is also presented.