Skip to Main Content
Through the research of an 8PSK demodulation algorithm including carrier phase recovery and clock timing recovery, an all-digital 8PSK demodulator adaptive to next generation digital satellite television standard DVB-S2 is proposed. The carrier recovery algorithm consists of a frequency detector (FD) loop and a modified phase-frequency detector (PFD) loop. Its tracking range exceeds one time symbol-rate. The Gardner TED algorithm is used in clock timing recovery loop. All algorithms are prone to hardware implementation. By means of analysis and computer fixed point simulation, the optimal parameter of each loop has been determined. The symbol error performance under AWGN is also presented. The result of simulations indicates that the demodulator performance of SER (symbol error rate) is close to theoretical value and the architecture is realizable.