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A novel VLSI architecture based on an improved lifting algorithm, which can be reconfigurable for 5/3 and 9/7 wavelet transforms, is proposed. The improved lifting algorithm, exploiting the parallelism of multiplication and addition operations based on the conventional lifting scheme, efficiently reduces the critical path delay. Systolic and the embedded pipeline techniques are adopted to optimize the design of the architecture, which significantly reduces the hardware complexity and power consumption of the design. Moreover, the proposed architecture works in a serial input fashion, with the result that the accessed memory needs only a single read port and a single write port, and can be easily extended to the implementation of a line-based architecture for 2D DWT.