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A formal verification methodology for IP-based designs

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3 Author(s)
D. Karlsson ; IDA, Linkopings universitet, Linkoping, Sweden ; P. Eles ; Z. Peng

This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design, using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already verified by their designers and which are considered correct under the assumption that the environment satisfies certain properties assumed by the component. What remains to be verified is the glue logic inserted between the components. Each such glue logic is verified one at a time using model checking techniques. Experiments, performed on a real-life example (mobile telephone), demonstrating the efficiency and intuitivity of the methodology, are moreover thoroughly presented. Three different properties have been verified on one part of the system.

Published in:

Digital System Design, 2004. DSD 2004. Euromicro Symposium on

Date of Conference:

31 Aug.-3 Sept. 2004