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The article is devoted to creating a complete methodology for automatic synthesis of real-time FFT-processors at structural level under the given restrictions: speed of input data receipt, structure of the computing element, and the time of the butterfly operation execution. The suggested approach involves creating parallel-pipeline structures for fixed radix FFT and for modified split radix FFT algorithms. The structures employed in the design show good possibilities for scaling the degree of parallelization, thus changing the overall throughput of the system. They are particularly suited for implementing in programmable logic basis (FPGA).
Date of Conference: 31 Aug.-3 Sept. 2004