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A proposed mechanism for super-pipelined instruction-issue for ILP stack machines

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1 Author(s)
Bailey, C. ; Dept. of Comput. Sci., York Univ., UK

A resurgence of interest in hardware stack-machine architectures, in which an implicitly addressed operand stack mode of computation is used, has followed closely in the wake of the growth of Java technology. However hardware for direct execution of stack-based machine level operations suffer from a lack of development in areas of advanced machine architecture, in particular where instruction-level parallelism is concerned. In this paper the author proposes a mechanism for super-pipelined issue of stack-based instructions to support an in-order issue policy with out-of-order completion, and introduces some preliminary results in order to illustrate possible trade-offs and issues likely to be valuable focal points for a full performance assessment in future work.

Published in:

Digital System Design, 2004. DSD 2004. Euromicro Symposium on

Date of Conference:

31 Aug.-3 Sept. 2004