Cart (Loading....) | Create Account
Close category search window
 

A 40 Gb/s network processor with PISC™ dataflow architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Carlstrom, J. ; Xelerated AB, Stockholm, Sweden ; Nordmark, G. ; Roos, J. ; Boden, T.
more authors

This 40 Gb/s network processor has a dataflow architecture with 200 PISC™ processors, organized in a linear array, also containing 11 I/O processors which interconnect to on-chip or off-chip engines. Implemented in a 0.13 μm CMOS process, the chip has 114M transistors and It typically dissipates 9.5 W at 200 MHz.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.