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A 40 Gb/s network processor with PISC™ dataflow architecture

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6 Author(s)
J. Carlstrom ; Xelerated AB, Stockholm, Sweden ; G. Nordmark ; J. Roos ; T. Boden
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This 40 Gb/s network processor has a dataflow architecture with 200 PISC™ processors, organized in a linear array, also containing 11 I/O processors which interconnect to on-chip or off-chip engines. Implemented in a 0.13 μm CMOS process, the chip has 114M transistors and It typically dissipates 9.5 W at 200 MHz.

Published in:

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

Date of Conference:

15-19 Feb. 2004