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In three decades, the IC industry grew from nothing to current GSI levels (with 109 devices on a chip). Its major driving force has been the use of device scaling, which has been especially effective in enhancing the performance of digital chips. However, increasingly, diverse system applications have created an additional driving force - the development of more and more system chips with an increased need to integrate more diverse functionality (digital, analog, memory, RF, etc.) within a limited form factor. In addition to current SoCs on a 2D die, a trend for the coming decade is multidimensional die integration on interconnected substrates in a compact package. Correspondingly, a metric analyzing technology trends is presented. At the same time, beyond the innovative foundry/fabless business structure of the 1990s, new business models are evolving for the realization of system chips. Such models, leading to an effective solution called virtual vertical integration, is discussed. System-chip development must also be vertically integrated to achieve optimized performance, but advanced technologies required to realize such integration cover various horizontal segments of knowledge, such as multidimensional-die architecture design, circuit design, and related design automation, as well as novel testing and packaging techniques, leading-edge device and wafer-fabrication technologies, and solution-oriented software coding. In this regard, critical challenges are highlighted in terms of power partitioning, integrated design, and built-in quality assurance for known-good-die, signal integrity in field applications, and technology optimization across different segments. The parallelism of technology solutions with business models, and their conjoined optimization in the coming system-chip era, is illustrated in this paper.
Date of Conference: 15-19 Feb. 2004