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ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

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3 Author(s)
Ming-Dou Ker ; Nanoelectronics & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Taiwan, Taiwan ; Chyh-Yih Chang ; Yi-Shu Chang

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 μm between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.

Published in:

Components and Packaging Technologies, IEEE Transactions on  (Volume:27 ,  Issue: 3 )

Date of Publication:

Sept. 2004

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