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Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design

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2 Author(s)
Ming-Dou Ker ; Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Kun-Hsien Lin

The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.

Published in:

IEEE Electron Device Letters  (Volume:25 ,  Issue: 9 )