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The re-use of complex digital signal processing (DSP) coprocessors can be improved using IP cores described at a high abstraction level. System integration, which is a major step in SoC design, requires taking into account communication and timing constraints to design and integrate IP. In this paper, we describe an IP design approach that relies on three main phases: constraints modeling, IP constraints analysis steps for feasibility checking, and synthesis. Based on a generic architecture, the presented method provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach in a case study of a maximum a posteriori (MAP) algorithm for a turbo decoder.