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Pipelining of parallel multiplexer loops and decision feedback equalizers

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1 Author(s)
Parhi, K.K. ; Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

The high speed implementation of a DFE (decision feedback equalizer) requires reformulation of the DFE into an array of comparators and a multiplexer loop. The throughput of the DFE is limited by the speed of the multiplexer loop. This paper proposes a novel look-ahead computation approach to pipeline multiplexer loops. The proposed technique is demonstrated and applied to design multiplexer loop based DFEs with throughput in the range of 3.125-10 Gbps.

Published in:

Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04). IEEE International Conference on  (Volume:5 )

Date of Conference:

17-21 May 2004

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