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Designing of precomputational-based low-power Viterbi decoder

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2 Author(s)
Jing-ling Yang ; Dept. of Electr. & Electron. Eng., Hong Kong Univ., China ; Wong, A.K.K.

This work addresses the low-power VLSI implementation of the Viterbi decoder (VD). A new precomputational scheme applied to the trellis butterflies calculation is presented. The proposed scheme is implemented in a 16-state, rate 1/3 VD. Gate-level power verification indicates that the proposed design reduces the power dissipated by the original trellis butterflies calculation by 42%.

Published in:

Emerging Technologies: Frontiers of Mobile and Wireless Communication, 2004. Proceedings of the IEEE 6th Circuits and Systems Symposium on  (Volume:2 )

Date of Conference:

31 May-2 June 2004