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A configurable two-dimensional (2-D) LFSR based test generator and an automated synthesis procedure are presented. Without storage of test patterns, a 2-D LFSR based test pattern generator can generate a sequence of precomputed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable faults). The hardware overhead is decreased considerably through configuration. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2-D LSFR can also be adopted in chip-level and system-on-a-chip (SoC) BIST.