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Low-latency virtual-channel routers for on-chip networks

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3 Author(s)
R. Mullins ; Comput. Lab., Cambridge Univ., UK ; A. West ; S. Moore

The on-chip communication requirements of many systems are best served through the deployment of a regular chip-wide network. This paper presents the design of a low-latency on-chip network router for such applications. We remove control overheads (routing and arbitration logic) from the critical path in order to minimise cycle-time and latency. Simulations illustrate that dramatic cycle time improvements are possible without compromising router efficiency. Furthermore, these reductions permit flits to be routed in a single cycle, maximising the effectiveness of the router's limited buffering resources.

Published in:

Computer Architecture, 2004. Proceedings. 31st Annual International Symposium on

Date of Conference:

19-23 June 2004