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A novel system for fully automated creation of layout, documentation and test programs for electrical test structures

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4 Author(s)
G. Leonardelli ; Yield Enhancement, Austriamicrosyst. AG, Vienna, Austria ; G. Roehrer ; R. Minixhofer ; M. Knaipp

Modern semiconductor processes have increasing complexity and thus an extremely high number of degrees of freedom. During the development of such a process a large number of test structures are necessary to understand the interaction of process parameters. In this paper we present a new method to streamline the information flow from development to layout and test.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004