Referenced Items are not available for this document.
Modern semiconductor processes have increasing complexity and thus an extremely high number of degrees of freedom. During the development of such a process a large number of test structures are necessary to understand the interaction of process parameters. In this paper we present a new method to streamline the information flow from development to layout and test.
Published in:
Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop
Date of Conference: 4-6 May 2004
- Page(s):
- 205 - 207
- Print ISBN:
- 0-7803-8312-5
- INSPEC Accession Number:
- 8082594
- Digital Object Identifier :
- 10.1109/ASMC.2004.1309566
- Product Type:
- Conference Publications
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