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Method for calculating high-resolution wafer parameter profiles

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2 Author(s)
Abercrombie, D. ; LSI Logic, Gresham, OR, USA ; Whitefield, B.

This paper describes a method to use parametric or yield data from many different products and die sizes for generating highly detailed wafer profiles. These profiles have an improved signal to noise ratio and spatial resolution compared to traditional wafer maps. This technique takes advantage of multiple die sizes and their variation in placement on the wafer to increase the information available about the wafer patterns. Several potential applications of these profiles were discussed.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004