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Optimizing pattern fill for planarity and parasitic capacitance

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8 Author(s)
M. Nelson ; AMI Semicond., Pocatello, ID, USA ; B. Williams ; C. Belisle ; S. Aytes
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In integrated circuit manufacturing with multi-level interconnect, it is important to have a planar surface preceding the next layer to avoid topography-induced patterning failure. In this paper, we describe a method for optimizing the use of pattern fill for planarity of CMP processing against the parasitic capacitive effects generated by such fill. Results applying this methodology on a seven metal product set are used to demonstrate its effectiveness.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004