Referenced Items are not available for this document.
In integrated circuit manufacturing with multi-level interconnect, it is important to have a planar surface preceding the next layer to avoid topography-induced patterning failure. In this paper, we describe a method for optimizing the use of pattern fill for planarity of CMP processing against the parasitic capacitive effects generated by such fill. Results applying this methodology on a seven metal product set are used to demonstrate its effectiveness.
Published in:
Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop
Date of Conference: 4-6 May 2004
- Page(s):
- 115 - 118
- Print ISBN:
- 0-7803-8312-5
- INSPEC Accession Number:
- 8072761
- Digital Object Identifier :
- 10.1109/ASMC.2004.1309547
- Product Type:
- Conference Publications
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