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Yield enhancement using recommended ground rules

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3 Author(s)
Maynard, D.N. ; IBM Microelectron. Div., Essex Junction, VT, USA ; Runyon, S.L. ; Reuter, B.B.

Recent years have seen interest in design for manufacturability (DFM) blossom in response to rapidly increasing technology and design complexity. Many semiconductor manufacturers have focused their efforts on productivity and, more specifically, yield. One yield enhancement technique is deployment of recommended ground rules (GRs), where the technology design manual advocates compliance with a number of "backed-off" GRs whenever practical to avoid difficult technology minimums. On the surface, this appears to be a common sense idea; however, in practice, actual exploitation of this DFM initiative in a product design poses many difficult questions. Ultimately, the designer must understand all trade-offs associated with the backed-off GRs to determine whether a productivity or reliability gain was realized. Attempting to understand specifically which set of recommended GRs to abide by (and where) further complicates the decision-making process. Identifying and defining recommended GRs is a significant challenge to process development engineering, since the chip design cycles often begin long before reliable manufacturing yield and performance data is available. This paper discusses these challenges, offers possible solutions, and illustrates with examples from the IBM Server Group's chips. These solutions include the use of sophisticated analysis and design checking tools to quantify the many alternatives. For example, the value of compliance with one GR might be weighed against the value of compliance with other, sometimes conflicting, rules, as well as performance, productivity, and other economic objectives. Therefore, an understanding of what physical or electrical problem the recommended GR is guarding against is necessary. The development picture of how these recommended GRs are determined is also explored, along with how final layouts are graded, and these concepts are tied together into a recommended business process.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004