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NPN transistor improvement by cumulative resist processing

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3 Author(s)
L. Szendrei ; Fairchild Semicond. Corp., South Portland, ME, USA ; S. Leibiger ; M. Doyle

A method for improving the performance of a single polysilicon NPN transistor by using cumulative/dual photoresist processing is presented. The photoresist from the polysilicon emitter layer patterning is preserved and over-coated in the subsequent extrinsic base implant masking layer. The n-type emitter polysilicon is thus protected from counter-doping by the p-type extrinsic base implantation in a self-aligned manner. Electrical consequences of applying this process, which include improved current gain and cutoff frequency, are reported.

Published in:

Advanced Semiconductor Manufacturing, 2004. ASMC '04. IEEE Conference and Workshop

Date of Conference:

4-6 May 2004