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A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-μm DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation.
Date of Publication: June 2004