Experience with interprocedural analysis of array side effects

The authors describe an implementation of regular section analysis in the Rice Parallel Fortran Converter (PFC), an automatic parallelization system. The overriding concern in the implementation is that it be efficient enough to be incorporated in a practical compilation system. This implementation of regular section analysis describes interprocedural side effects on subarrays in a form useful to dependence analysis while avoiding the complexity of prior solutions. The authors also examine the performance of regular section analysis on two benchmarks: the LINPACK library of linear algebra subroutines and the Rice Compiler Evaluation Program Suite, a set of complete application codes from a variety of scientific disciplines. It is demonstrated that regular section analysis is an effective means of discovering parallelism, given programs written in an appropriately modular programming style.<
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