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Optimal loop scheduling with register constraints using flow graphs

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3 Author(s)
Muller, J. ; Dept. of Electr. Eng., Dresden Univ. of Technol., Germany ; Fimmel, D. ; Merker, R.

We present a novel loop scheduling approach using a generalized flow graph model of the resource constraints. From this model we derive a new flow graph to incorporate register constraints. Our linear programming implementation produces an optimum loop schedule, respecting the constraints on functional units and registers in a single optimization problem. Moreover, the iteration interval is treated as a rational number, and the approach supports heterogeneous processor architectures and pipelined functional units. Compared to earlier approaches, the solution can reduce the problem complexity and solution time, and provide faster loop schedules.

Published in:

Parallel Architectures, Algorithms and Networks, 2004. Proceedings. 7th International Symposium on

Date of Conference:

10-12 May 2004