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A channel based asynchronous low power high performance standard-cell based sequential decoder implemented with QDI templates

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2 Author(s)
Ozdag, R.O. ; Dept. of Electr. Eng. Syst., Southern California Univ., Los Angeles, CA, USA ; Beerel, P.A.

This work presents the design of a channel-based asynchronous sequential decoder implemented with quasi-delay-insensitive templates. The Powermill© simulation results in TSMC 0.25 CMOS technology show that the circuit runs at 430MHz and consumes 32mW. Techniques to effectively partition and implement the top-level design, the implementation of fast shift registers, memories, and various other structures are discussed. Compared to a previously designed synchronous Fano decoder, the asynchronous version consumes 1/3 the power and runs at 2.15 times the speed assuming standard process normalization. The design also highlights the introduction of a standard-cell library and back-end design flow for asynchronous designs based on PCHB templates.

Published in:

Asynchronous Circuits and Systems, 2004. Proceedings. 10th International Symposium on

Date of Conference:

19-23 April 2004

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